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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle"><div class="title">GICDistributor_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__Core__FunctionInterface.html">Core Peripherals</a> &raquo; <a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></div></div></div>
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<p>Structure type to access the Generic Interrupt Controller Distributor (GICD)  
 <a href="structGICDistributor__Type.html#details">More...</a></p>

<p><code>#include &lt;core_ca.h&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a6ca67d9838ab3425864207c3a0399bd7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a></td></tr>
<tr class="memdesc:a6ca67d9838ab3425864207c3a0399bd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Distributor Control Register.  <br /></td></tr>
<tr class="separator:a6ca67d9838ab3425864207c3a0399bd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a405823d97dc90dd9d397a3980e2cd207"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207">TYPER</a></td></tr>
<tr class="memdesc:a405823d97dc90dd9d397a3980e2cd207"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/ ) Interrupt Controller Type Register.  <br /></td></tr>
<tr class="separator:a405823d97dc90dd9d397a3980e2cd207"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acebf65dae4cb82cd3c7deeefca9c9722"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">IIDR</a></td></tr>
<tr class="memdesc:acebf65dae4cb82cd3c7deeefca9c9722"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/ ) Distributor Implementer Identification Register.  <br /></td></tr>
<tr class="separator:acebf65dae4cb82cd3c7deeefca9c9722"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae24f260e27065660a2059803293084f2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2">STATUSR</a></td></tr>
<tr class="memdesc:ae24f260e27065660a2059803293084f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) Error Reporting Status Register, optional.  <br /></td></tr>
<tr class="separator:ae24f260e27065660a2059803293084f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afbdd372578e2cd6f998320282cc8ed25"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25">SETSPI_NSR</a></td></tr>
<tr class="memdesc:afbdd372578e2cd6f998320282cc8ed25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 ( /W) Set SPI Register.  <br /></td></tr>
<tr class="separator:afbdd372578e2cd6f998320282cc8ed25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f584d3fbeaa355faf234f2ee57d1168"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">CLRSPI_NSR</a></td></tr>
<tr class="memdesc:a2f584d3fbeaa355faf234f2ee57d1168"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 ( /W) Clear SPI Register.  <br /></td></tr>
<tr class="separator:a2f584d3fbeaa355faf234f2ee57d1168"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ad55a8644bc95caf8bf53e1407ec9ed0c">SETSPI_SR</a></td></tr>
<tr class="memdesc:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 ( /W) Set SPI, Secure Register.  <br /></td></tr>
<tr class="separator:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab487e4a8684b8a77357c6c20cf71dead"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ab487e4a8684b8a77357c6c20cf71dead">CLRSPI_SR</a></td></tr>
<tr class="memdesc:ab487e4a8684b8a77357c6c20cf71dead"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x058 ( /W) Clear SPI, Secure Register.  <br /></td></tr>
<tr class="separator:ab487e4a8684b8a77357c6c20cf71dead"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a9effdd633c6e75651d9f53caace306"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">IGROUPR</a> [32]</td></tr>
<tr class="memdesc:a6a9effdd633c6e75651d9f53caace306"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Group Registers.  <br /></td></tr>
<tr class="separator:a6a9effdd633c6e75651d9f53caace306"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1da3a2066b64644a0bb8a3066075ba87"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">ISENABLER</a> [32]</td></tr>
<tr class="memdesc:a1da3a2066b64644a0bb8a3066075ba87"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set-Enable Registers.  <br /></td></tr>
<tr class="separator:a1da3a2066b64644a0bb8a3066075ba87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a390fa9f2f460951b2c6094932d890807"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">ICENABLER</a> [32]</td></tr>
<tr class="memdesc:a390fa9f2f460951b2c6094932d890807"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear-Enable Registers.  <br /></td></tr>
<tr class="separator:a390fa9f2f460951b2c6094932d890807"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c15cd75ce30d8946792e2a1a19556a5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">ISPENDR</a> [32]</td></tr>
<tr class="memdesc:a1c15cd75ce30d8946792e2a1a19556a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Set-Pending Registers.  <br /></td></tr>
<tr class="separator:a1c15cd75ce30d8946792e2a1a19556a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0155cb4637845258e4ee76cd93cca2a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">ICPENDR</a> [32]</td></tr>
<tr class="memdesc:a0155cb4637845258e4ee76cd93cca2a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x280 (R/W) Interrupt Clear-Pending Registers.  <br /></td></tr>
<tr class="separator:a0155cb4637845258e4ee76cd93cca2a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">ISACTIVER</a> [32]</td></tr>
<tr class="memdesc:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Set-Active Registers.  <br /></td></tr>
<tr class="separator:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">ICACTIVER</a> [32]</td></tr>
<tr class="memdesc:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x380 (R/W) Interrupt Clear-Active Registers.  <br /></td></tr>
<tr class="separator:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a08fa902293567e85dc6398dab58afaa9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">IPRIORITYR</a> [255]</td></tr>
<tr class="memdesc:a08fa902293567e85dc6398dab58afaa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x400 (R/W) Interrupt Priority Registers.  <br /></td></tr>
<tr class="separator:a08fa902293567e85dc6398dab58afaa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f1b07d48d3a9199f2effec8492f721c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> [255]</td></tr>
<tr class="memdesc:a6f1b07d48d3a9199f2effec8492f721c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x800 (R/W) Interrupt Targets Registers.  <br /></td></tr>
<tr class="separator:a6f1b07d48d3a9199f2effec8492f721c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b306a630388c795d3cd32fc2e23a2b5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5">ICFGR</a> [64]</td></tr>
<tr class="memdesc:a9b306a630388c795d3cd32fc2e23a2b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xC00 (R/W) Interrupt Configuration Registers.  <br /></td></tr>
<tr class="separator:a9b306a630388c795d3cd32fc2e23a2b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9eeb19ca95d0b95828f1f98700b5689"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">IGRPMODR</a> [32]</td></tr>
<tr class="memdesc:ae9eeb19ca95d0b95828f1f98700b5689"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xD00 (R/W) Interrupt Group Modifier Registers.  <br /></td></tr>
<tr class="separator:ae9eeb19ca95d0b95828f1f98700b5689"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a644abefb7064e434db20cc6dab5fe5f1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a644abefb7064e434db20cc6dab5fe5f1">NSACR</a> [64]</td></tr>
<tr class="memdesc:a644abefb7064e434db20cc6dab5fe5f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xE00 (R/W) Non-secure Access Control Registers.  <br /></td></tr>
<tr class="separator:a644abefb7064e434db20cc6dab5fe5f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6ac65c4a5394926cc9518753a00d4da1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1">SGIR</a></td></tr>
<tr class="memdesc:a6ac65c4a5394926cc9518753a00d4da1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xF00 ( /W) Software Generated Interrupt Register.  <br /></td></tr>
<tr class="separator:a6ac65c4a5394926cc9518753a00d4da1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a644a70cf4c12093c0277ce01f194b69b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b">CPENDSGIR</a> [4]</td></tr>
<tr class="memdesc:a644a70cf4c12093c0277ce01f194b69b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xF10 (R/W) SGI Clear-Pending Registers.  <br /></td></tr>
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<tr class="memdesc:ae40b4a50d9766c2bbf57441f68094f41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xF20 (R/W) SGI Set-Pending Registers.  <br /></td></tr>
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<tr class="memdesc:a73e0c679e5f45710deea474ab0d39cdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x6100(R/W) Interrupt Routing Registers.  <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure type to access the Generic Interrupt Controller Distributor (GICD) </p>
</div><h2 class="groupheader">Field Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a2f584d3fbeaa355faf234f2ee57d1168">&#9670;&#160;</a></span>CLRSPI_NSR</h2>

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          <td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::CLRSPI_NSR</td>
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<p>Offset: 0x048 ( /W) Clear SPI Register. </p>
<p>Clear Non-secure SPI Pending Register</p>
<table class="markdownTable">
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[9:0]   </td><td class="markdownTableBodyLeft">INTID   </td><td class="markdownTableBodyLeft">The interrupt number to clear pending state from.   </td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#ab487e4a8684b8a77357c6c20cf71dead">&#9670;&#160;</a></span>CLRSPI_SR</h2>

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          <td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::CLRSPI_SR</td>
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<p>Offset: 0x058 ( /W) Clear SPI, Secure Register. </p>
<p>Clear Secure SPI Pending Register</p>
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[9:0]   </td><td class="markdownTableBodyLeft">INTID   </td><td class="markdownTableBodyLeft">The interrupt number to clear pending state from.   </td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a644a70cf4c12093c0277ce01f194b69b">&#9670;&#160;</a></span>CPENDSGIR</h2>

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<p>Offset: 0xF10 (R/W) SGI Clear-Pending Registers. </p>
<p>SGI Clear-Pending Registers Each register corresponds to one software generated interrupt (SGI).</p>
<p>Reading from this register reveals</p><ul>
<li>0 - interrupt is not pending</li>
<li>1 - interrupt is pending</li>
</ul>
<p>Writing to this register causes</p><ul>
<li>0 - no effect</li>
<li>1 - removes the pending state </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#a6ca67d9838ab3425864207c3a0399bd7">&#9670;&#160;</a></span>CTLR</h2>

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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::CTLR</td>
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<p>Offset: 0x000 (R/W) Distributor Control Register. </p>
<p>Distributor Control Register</p>
<p>When access is Secure, in a system that supports two Security states:</p>
<table class="markdownTable">
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<td class="markdownTableBodyLeft">[31]   </td><td class="markdownTableBodyLeft">RWP   </td><td class="markdownTableBodyLeft">Indicates whether a register write is in progress or not.    </td></tr>
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<td class="markdownTableBodyLeft">[30:8]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EINWF   </td><td class="markdownTableBodyLeft">Enable 1 of N Wakeup Functionality, if available.    </td></tr>
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<td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">DS   </td><td class="markdownTableBodyLeft">Disable Security.    </td></tr>
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<td class="markdownTableBodyLeft">[5]   </td><td class="markdownTableBodyLeft">ARE_NS   </td><td class="markdownTableBodyLeft">Affinity Routing Enable, Non-secure state.    </td></tr>
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<td class="markdownTableBodyLeft">[4]   </td><td class="markdownTableBodyLeft">ARE_S   </td><td class="markdownTableBodyLeft">Affinity Routing Enable, Secure state.    </td></tr>
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<td class="markdownTableBodyLeft">[3]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[2]   </td><td class="markdownTableBodyLeft">EnableGrp1S   </td><td class="markdownTableBodyLeft">Enable Secure Group 1 interrupts.    </td></tr>
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<td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">EnableGrp1NS   </td><td class="markdownTableBodyLeft">Enable Non-secure Group 1 interrupts.    </td></tr>
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<td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">EnableGrp0   </td><td class="markdownTableBodyLeft">Enable Group 0 interrupts.   </td></tr>
</table>
<p>When access is Non-secure, in a system that supports two Security states:</p>
<table class="markdownTable">
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31]   </td><td class="markdownTableBodyLeft">RWP   </td><td class="markdownTableBodyLeft">Indicates whether a register write is in progress or not.    </td></tr>
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<td class="markdownTableBodyLeft">[30:5]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[4]   </td><td class="markdownTableBodyLeft">ARE_NS   </td><td class="markdownTableBodyLeft">Affinity Routing Enable, Non-secure state.    </td></tr>
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<td class="markdownTableBodyLeft">[3:2]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">EnableGrp1A   </td><td class="markdownTableBodyLeft">Enable Non-secure Group 1 interrupts.    </td></tr>
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<td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">EnableGrp1   </td><td class="markdownTableBodyLeft">Enable Non-secure Group 1 interrupts.   </td></tr>
</table>
<p>When in a system that supports only a single Security state:</p>
<table class="markdownTable">
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<td class="markdownTableBodyLeft">[31]   </td><td class="markdownTableBodyLeft">RWP   </td><td class="markdownTableBodyLeft">Indicates whether a register write is in progress or not.    </td></tr>
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<td class="markdownTableBodyLeft">[30:8]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EINWF   </td><td class="markdownTableBodyLeft">Enable 1 of N Wakeup Functionality, if available.    </td></tr>
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<td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">DS   </td><td class="markdownTableBodyLeft">Disable Security.    </td></tr>
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<td class="markdownTableBodyLeft">[5]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[4]   </td><td class="markdownTableBodyLeft">ARE   </td><td class="markdownTableBodyLeft">Affinity Routing Enable.    </td></tr>
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<td class="markdownTableBodyLeft">[3:2]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">EnableGrp1   </td><td class="markdownTableBodyLeft">Enable Group 1 interrupts.    </td></tr>
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<td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">EnableGrp0   </td><td class="markdownTableBodyLeft">Enable Group 0 interrupts.   </td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#ac0fd4c1ad19b5a332e403bb9966ba967">&#9670;&#160;</a></span>ICACTIVER</h2>

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<p>Offset: 0x380 (R/W) Interrupt Clear-Active Registers. </p>
<p>Interrupt Clear-Active Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Offset: 0x180 (R/W) Interrupt Clear-Enable Registers. </p>
<p>Interrupt Clear-Enable Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#a9b306a630388c795d3cd32fc2e23a2b5">&#9670;&#160;</a></span>ICFGR</h2>

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<p>Offset: 0xC00 (R/W) Interrupt Configuration Registers. </p>
<p>Interrupt Configuration Registers</p>
<p>Each interrupt can be configured by two corresponding bits:</p>
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<td class="markdownTableBodyLeft">[2*INTID%16+1]   </td><td class="markdownTableBodyLeft">Edge   </td><td class="markdownTableBodyLeft">Interrupt is: 0 - level sensitive, 1 - edge triggered    </td></tr>
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<td class="markdownTableBodyLeft">[2*INTID%16]   </td><td class="markdownTableBodyLeft">Model   </td><td class="markdownTableBodyLeft">0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported   </td></tr>
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<p>Offset: 0x280 (R/W) Interrupt Clear-Pending Registers. </p>
<p>Interrupt Clear-Pending Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Offset: 0x080 (R/W) Interrupt Group Registers. </p>
<p>Interrupt Group Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<p>And the value denotes:</p><ul>
<li>0 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==1, the corresponding interrupt is Group 0<br  />
 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==0, the corresponding interrupt is Secure.</li>
<li>1 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==1, the corresponding interrupt is Group 1.<br  />
 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==0, the corresponding interrupt is Non-secure Group 1. </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#ae9eeb19ca95d0b95828f1f98700b5689">&#9670;&#160;</a></span>IGRPMODR</h2>

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<p>Offset: 0xD00 (R/W) Interrupt Group Modifier Registers. </p>
<p>Interrupt Group Modifier Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32 </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#acebf65dae4cb82cd3c7deeefca9c9722">&#9670;&#160;</a></span>IIDR</h2>

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<p>Offset: 0x008 (R/ ) Distributor Implementer Identification Register. </p>
<p>Distributor Implementer Identification Register</p>
<table class="markdownTable">
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:24]   </td><td class="markdownTableBodyLeft">ProductID   </td><td class="markdownTableBodyLeft">An IMPLEMENTATION DEFINED product identifier    </td></tr>
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<td class="markdownTableBodyLeft">[23:20]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[19:16]   </td><td class="markdownTableBodyLeft">Variant   </td><td class="markdownTableBodyLeft">An IMPLEMENTATION DEFINED variant number.    </td></tr>
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<td class="markdownTableBodyLeft">[15:12]   </td><td class="markdownTableBodyLeft">Revision   </td><td class="markdownTableBodyLeft">An IMPLEMENTATION DEFINED revision number.    </td></tr>
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<td class="markdownTableBodyLeft">[11:0]   </td><td class="markdownTableBodyLeft">Implementer   </td><td class="markdownTableBodyLeft">Contains the JEP106 code of the company implemented the GICD.   </td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a08fa902293567e85dc6398dab58afaa9">&#9670;&#160;</a></span>IPRIORITYR</h2>

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<p>Offset: 0x400 (R/W) Interrupt Priority Registers. </p>
<p>Interrupt Priority Registers</p>
<p>A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI.</p>
<dl class="section note"><dt>Note</dt><dd>A register field corresponding to an unimplemented interrupt is RAZ/WI. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#a73e0c679e5f45710deea474ab0d39cdb">&#9670;&#160;</a></span>IROUTER</h2>

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<p>Offset: 0x6100(R/W) Interrupt Routing Registers. </p>
<p>Interrupt Routing Registers</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[63:40]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">[39:32]   </td><td class="markdownTableBodyLeft">Aff3   </td><td class="markdownTableBodyLeft">Affinity level 3, the least significant affinity level field.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">[31]   </td><td class="markdownTableBodyLeft">IRM   </td><td class="markdownTableBodyLeft">Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">[30:24]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">[23:16]   </td><td class="markdownTableBodyLeft">Aff2   </td><td class="markdownTableBodyLeft">Affinity level 2, an intermediate affinity level field.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">[15:8]   </td><td class="markdownTableBodyLeft">Aff1   </td><td class="markdownTableBodyLeft">Affinity level 1, an intermediate affinity level field.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">[7:0]   </td><td class="markdownTableBodyLeft">Aff0   </td><td class="markdownTableBodyLeft">Affinity level 0, the most significant affinity level field.   </td></tr>
</table>

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<p>Offset: 0x300 (R/W) Interrupt Set-Active Registers. </p>
<p>Interrupt Set-Active Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Offset: 0x100 (R/W) Interrupt Set-Enable Registers. </p>
<p>Interrupt Set-Enable Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Offset: 0x200 (R/W) Interrupt Set-Pending Registers. </p>
<p>Interrupt Set-Pending Registers</p>
<p>Each bit corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Offset: 0x800 (R/W) Interrupt Targets Registers. </p>
<p>Interrupt Processor Targets Registers</p>
<p>Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI.</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadLeft">CPU target field value   </th><th class="markdownTableHeadLeft">Interrupt targets    </th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">0bxxxxxxx1   </td><td class="markdownTableBodyLeft">CPU interface 0    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">0bxxxxxx1x   </td><td class="markdownTableBodyLeft">CPU interface 1    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">0bxxxxx1xx   </td><td class="markdownTableBodyLeft">CPU interface 2    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">0bxxxx1xxx   </td><td class="markdownTableBodyLeft">CPU interface 3    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">0bxxx1xxxx   </td><td class="markdownTableBodyLeft">CPU interface 4    </td></tr>
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<td class="markdownTableBodyLeft">0bxx1xxxxx   </td><td class="markdownTableBodyLeft">CPU interface 5    </td></tr>
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<td class="markdownTableBodyLeft">0bx1xxxxxx   </td><td class="markdownTableBodyLeft">CPU interface 6    </td></tr>
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<td class="markdownTableBodyLeft">0b1xxxxxxx   </td><td class="markdownTableBodyLeft">CPU interface 7   </td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#a644abefb7064e434db20cc6dab5fe5f1">&#9670;&#160;</a></span>NSACR</h2>

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<p>Offset: 0xE00 (R/W) Non-secure Access Control Registers. </p>
<p>Non-secure Access Control Registers</p>
<p>Each two bits corresponds to one interrupt:</p><ul>
<li>Register index is given by INTID/16</li>
<li>Bit number is given by 2*INTID%16</li>
</ul>
<p>The possible values of each 2-bit field are:</p><ul>
<li>00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.</li>
<li>01 - Non-secure accesses are only permitted to requesting fields.</li>
<li>10 - As 01, additionally accesses to clearing field are permitted.</li>
<li>11 - As 10, additionally accesses to target and routing fields are permitted. </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#afbdd372578e2cd6f998320282cc8ed25">&#9670;&#160;</a></span>SETSPI_NSR</h2>

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<p>Offset: 0x040 ( /W) Set SPI Register. </p>
<p>Set Non-secure SPI Pending Register</p>
<table class="markdownTable">
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[9:0]   </td><td class="markdownTableBodyLeft">INTID   </td><td class="markdownTableBodyLeft">The interrupt number to set pending state for.   </td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#ad55a8644bc95caf8bf53e1407ec9ed0c">&#9670;&#160;</a></span>SETSPI_SR</h2>

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<p>Offset: 0x050 ( /W) Set SPI, Secure Register. </p>
<p>Set Secure SPI Pending Register</p>
<table class="markdownTable">
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[9:0]   </td><td class="markdownTableBodyLeft">INTID   </td><td class="markdownTableBodyLeft">The interrupt number to set pending state for.   </td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#a6ac65c4a5394926cc9518753a00d4da1">&#9670;&#160;</a></span>SGIR</h2>

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<p>Offset: 0xF00 ( /W) Software Generated Interrupt Register. </p>
<p>Software Generated Interrupt Register</p>
<table class="markdownTable">
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<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:26]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[25:24]   </td><td class="markdownTableBodyLeft">TargetFilterList   </td><td class="markdownTableBodyLeft">Determines how the Distributor processes the requested SGI.    </td></tr>
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<td class="markdownTableBodyLeft">[23:16]   </td><td class="markdownTableBodyLeft">CPUTargetList   </td><td class="markdownTableBodyLeft">When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt.    </td></tr>
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<td class="markdownTableBodyLeft">[15]   </td><td class="markdownTableBodyLeft">NSATT   </td><td class="markdownTableBodyLeft">Specifies the required group of the SGI.    </td></tr>
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<td class="markdownTableBodyLeft">[14:4]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[3:0]   </td><td class="markdownTableBodyLeft">INTID   </td><td class="markdownTableBodyLeft">The INTID of the SGI to forward to the specified CPU interfaces.   </td></tr>
</table>
<p>Refer to <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> for details on TargetFilterList field. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae40b4a50d9766c2bbf57441f68094f41">&#9670;&#160;</a></span>SPENDSGIR</h2>

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<p>Offset: 0xF20 (R/W) SGI Set-Pending Registers. </p>
<p>SGI Set-Pending Registers Each register corresponds to one software generated interrupt (SGI).</p>
<p>Reading from this register reveals</p><ul>
<li>0 - interrupt is not pending</li>
<li>1 - interrupt is pending</li>
</ul>
<p>Writing to this register causes</p><ul>
<li>0 - no effect</li>
<li>1 - adds the pending state </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#ae24f260e27065660a2059803293084f2">&#9670;&#160;</a></span>STATUSR</h2>

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<p>Offset: 0x010 (R/W) Error Reporting Status Register, optional. </p>
<p>Error Reporting Status Register</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:4]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[3]   </td><td class="markdownTableBodyLeft">WROD   </td><td class="markdownTableBodyLeft">Write to an RO location.    </td></tr>
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<td class="markdownTableBodyLeft">[2]   </td><td class="markdownTableBodyLeft">RWOD   </td><td class="markdownTableBodyLeft">Read of a WO location.    </td></tr>
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<td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">WRD   </td><td class="markdownTableBodyLeft">Write to a reserved location.    </td></tr>
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<td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">RRD   </td><td class="markdownTableBodyLeft">Read of a reserved location.   </td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#a405823d97dc90dd9d397a3980e2cd207">&#9670;&#160;</a></span>TYPER</h2>

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<p>Offset: 0x004 (R/ ) Interrupt Controller Type Register. </p>
<p>Interrupt Controller Type Register</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
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<td class="markdownTableBodyLeft">[31:16]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
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<td class="markdownTableBodyLeft">[15:11]   </td><td class="markdownTableBodyLeft">LSPI   </td><td class="markdownTableBodyLeft">Maximum number of lockable shared interrupts.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">SecurityExtn   </td><td class="markdownTableBodyLeft">Security Extensions: 0 - not implemented. 1 - implemented.    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">[9:8]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">[7:5]   </td><td class="markdownTableBodyLeft">CPUNumber   </td><td class="markdownTableBodyLeft">Number of implemented CPU interfaces [=CPUNumber+1]    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft">[4:0]   </td><td class="markdownTableBodyLeft">ITLinesNumber   </td><td class="markdownTableBodyLeft">Maximum number of interrups supported [=32*(ITLinesNumber+1)].   </td></tr>
</table>

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